1. Field of the Invention
This invention relates to transmission of digital image data sent from a computing device to a display device and, more particularly, to an on-chip termination circuit for terminating a line transmitting the digital image data from the computing device to the display device for eventual visual display.
2. Description of the Prior Art
A personal computing device transmits digital image data to an attached display device through a transmission line for eventual visual display. An ideal transmission line will deliver the image data signal to the display without any loss or corruption. Practical transmission lines, however, are not ideal.
To minimize distortion of the transmitted digital data, the transmission line requires proper transmission line termination. If the transmission line is not terminated with its characteristic impedance, the input impedance may become complex and exhibit inductive or capacitive characteristics depending on the nature of the load, its electrical distance from the source, or the measure of termination resistance.
If a mismatch occurs between the line""s characteristic impedance and the termination resistance as the image data signal travels down the transmission line, a portion of the image data signal is reflected toward the computing device. The reflected wave combines with the forward wave and alters it according to its relative phase and amplitude, corrupting the image data. To avoid impedance mismatches, transmission lines must be terminated commonly with precise termination resistances having tight tolerances typically around 5% or better.
Transmission line termination is typically achieved through fixed, discrete, off-chip, precision resistors that accurately match the transmission line characteristic impedance. Off-chip precision resistors having tight tolerances are readily available. But they require significant circuit board space increasing circuit board layout complexity and cost.
Transmission line termination is particularly challenging when working with resistances built into semiconductor integrated circuits (on-chip). On-chip termination resistances are difficult to manufacture with tight tolerances. On-chip resistors typically show a variation as much as 15-20% or worse over process and temperature. Precision on-chip resistors are difficult to achieve with high volume semiconductor processing methods, for example, because of variations in sheet resistance and line width control. Furthermore, many applications use high-density digital Complementary Metal Oxide Semiconductor (CMOS) technology for high speed. As speed performance improves, process elements such as poly and moat resistors are often unavailable to circuit designers because of the use of silicide to minimize sheet resistances. Thus, to create resistors, additional mask levels, or the use of analog specific processes, are required.
An alternative technique for implementing termination resistors on a CMOS integrated circuit is to bias a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) into the triode region. FIG. 1 is a typical output characteristic of a MOSFET device in which two regions of operation are shown: the triode region and the saturation region. A MOSFET device biased in the triode region operates similarly to an ideal resistor as shown in FIG. 1 where the drain current is approximately linearly proportional to the drain-source voltage. As the drain source voltage increases, however, the MOSFET device""s resistance exhibits non-linearity with respect to drain-source voltage. This non-linearity results in operation that deviates from the ideal resistor. More specifically, the differential or small signal MOSFET resistance given by dVDS/dID, changes as the voltage across the drain and source of the MOSFET changes. This change in differential resistance is large enough to be problematic in many applications, including image data transmission, where it can cause impedance mismatch resulting in bit errors.
Accordingly, a need remains for an inexpensive and effective on-chip termination circuit that prevents impedance mismatches in transmission line circuits by exhibiting superior linearity and tight manufacturing tolerances.